Differential IO Buffer (CLN12FFC)
差分IO缓冲器 (TSMC 12nm FFC)
Analog Bits’ Differential IO Buffer macros provide a low noise, high performance differential output clock that is compatible with HCSL (Host Controller Signal Level) timing applications. The output buffer design implements a current steering logic differential driver which provides a standard voltage output differential (VOD) up to 700mV for support of PCI-Express clocking solutions. The differential input buffer can also be used for receiving a reference clock in a PCI-Express PHY application.
The IO buffer is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. There are no power-up/power-off sequence restrictions on the Core (0.8V) and IO (1.8V) supplies although datasheet functionality are only valid with all power supplies and control signals with normal operating ranges. The IO buffer is designed as a bi-direction IO but not intended for dynamic IO configuration.
The IO buffers include VDD and VD18 power detectors, which automatically shut down the macro when either rail is not up. An aPowerGood control pin is also implemented to manually power off the macro when any power supply is not stable.
The IO buffers are presented as two macros ABJBCHLB and ABJBCHLR. ABJBCHLB is the actual IO buffer which can be instantiated multiple times. ABJBCHLR generates the reference voltages/currents required by ABJBCHLB transmit mode and connections between the macros are achieved by abutment.
Figure 1: Differential IO Buffer with Reference Buffer Block Diagram
Pin Description for ABJBCHLB
Pin Description for ABJBCHLR
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