Low Power Frac-N (CLN12FFC)
低功耗小数分频锁相环 (TSMC 12nm FFC)
· Electrically Programmable PLL for multiple applications
· Ability to generate precise system clocks synchronized to track remote sources
· Very fine precision: near 1 part per billion resolution
· Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
· Implemented with Analog Bits’ proprietary architecture
· Fully integrated inside industry standard or other customized IO ring
· Occupies zero core area
· Low power consumption
· Spread Spectrum tracking capability
· Requires no additional on-chip components or band-gaps, minimizing power consumption
Analog Bits’ low power Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking or fine tuning on-the-fly. The PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by and operational power.
PLL Operational Range
Figure 1: PLL Block Diagram
PLL Pin Description
The PLL accepts a wide range of input frequencies and can produce a wide range of output frequencies, as described in Table 1. Several control bits are provided to configure the desired operating mode of the PLL.
A LOCK signal is provided to indicate that the PLL has locked on to the incoming signal. A RESET control is provided to power down the PLL and reset it to a known state. A BYPASS signal is provided which both powers-down the PLL and bypasses it such that PLLOUT tracks REF. Either BYPASS or RESET may be used for power-down IDDQ testing.
Deliverables and EDA Design Views