Low Power Frac-N SSCG (CLN7FF)
低功耗小数分频锁相环 (TSMC 7nm FF)
· Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
· Wide Ranges of Input and Output Frequency for diverse clocking needs
· Very fine precision: near 1 part per billion resolution
· Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
· Ability to generate precise system clocks synchronized to track remote sources
· Implemented with Analog Bits’ proprietary architecture
· Low power consumption
· Small area footprint
· Excellent jitter performance with optimized noise rejection
Analog Bits’ low power Fractional-N SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking or fine tuning on-the-fly. The PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.
The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.
Furthermore, it is a requirement by the FCC and equivalent international bodies that electronic devices including game-consoles, PCs, and high speed compute servers, limit Electromagnetic Interference (EMI) when they operate. The Spread Spectrum function of the PLL is capable of generating precise clock spreads (using a triangular modulation profile) that help reduce EMI. Programmable options allow the user to control the degree of spread in fine steps of modulation frequency and depth.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by and operational power.
PLL Operational Range
Fractional-N / SSCG PLL Block Diagram
Spread Spectrum Modulation Modes
PLL Pin Description