Power-On Reset (CLN12FFC)
上电复位IP (TSMC 12nm FFC)
· Integrated voltage and time references for precision stand-alone operation
· Easy to integrate with no additional component or special power requirements
· Easy to use and configure
· Programmable hysteresis, with independent programming available for power-on and power-off levels,
· Programmable delay feature to assure power supply settling
· Implemented with Analog Bits’ proprietary architecture
· Requires no additional on-chip components, minimizing power consumption
Analog Bits’ Power-On Reset (POR) macro comprehensively addresses typical SOC start-up power supply monitoring needs, in a fully integrated easy-to-use macro. The POR includes an internal bandgap style voltage reference circuit which is used as a reference to compare the power supplies against. The POR further includes its own timebase reference circuit, so requires no clock or other synchronizing signal to work correctly. Only when both IO and Core power supplies have both exceeded a user-selected voltage level for a user-selected time, will the outputs signal that power is good.
The POR provides outputs at both the IO and core logic levels, with a low level representing a poor or unstable power supply, and a high level representing a good stable power supply. These signals may be used as logical “RSB” or “ENA” signals.
Power-On Reset Block Diagram
Deliverables and EDA Design Views